USB-C Connectivity
WT61F201
【 General Description 】 |
WT61F201 is a dual-port USB/PD Controller with 128KB embedded Flash and 4KB SRAM, which is compliant with USB Power Delivery 3.1 supporting all standard power profiles. It provides the USB PD communication for two USB-C ports and one USB Billboard Device Class for USB-C applications. Also, USB-C Charging Upstream-facing Port (UFP), Dual Role Power (DRP) with Fast Role Swap (FRS), DP Alt-mode Configuration, USB Billboard Device and In-System-Programming (ISP) through USB-C are supported. |
With rich functions in one chip, the WT61F201 is suitable for applications such as video adapters, multi-function docking stations, dongles, power banks, and monitors. |
【 Features 】 | |
● | Supports dual port USB-C; CC0_A/CC0_B and CC1_A/CC1_B |
● | CC Logic and PD3.1 Engine supporting one Charging Upstream-facing Port (UFP) and one Dual Role Power (DRP) with Fast Role Swap (FRS) |
-Built-in pull-up/pull-down resistors (Rp and Rd) | |
● | USB-C Charging UFP Capability |
-Charging connected PD hosts once external power is available | |
-Supports Provider and Consumer roles | |
-Support PD Power Rule up to 140W | |
-Support dead battery charging and FRS | |
● | USB-C DRP Capability |
-Supports Provider and Consumer roles | |
-Support PD Power Rule up to 140W as Sink and 140W as Source | |
● | DP Alt-mode Configuration |
-Built-in Aux_CH switch | |
● | Supports USB Billboard Device |
● | In-System-Programming (ISP) through USB-C |
● | Supports DP 1.4 pass through |
● | On-chip Full-Speed USB Slave which is compliant to USB 2.0 Specification |
● | MCU Subsystem |
-8051 core with 128K bytes Flash, 256 bytes Direct RAM and 4K bytes on-chip auxiliary RAM | |
-Fast CPU rate (24Mhz). 41.6 ns for shortest instruction | |
-Programmable CPU clocks from 24 Mhz to 500 Khz | |
-Programmable crystal start-up cycles from 0 to 4096 cycles | |
-Supports Idle mode and Stop mode for power saving | |
-Supports crystal/CPU wake-up from Stop mode | |
-Up to 26 GPIOs | |
-Supports external interrupts on 2 GPIO pins | |
-Supports keyboard interrupt on 4 GPIO pins | |
-4 Timers; On-chip 15-bit programmable Watchdog Timer | |
-Serial Port supports Synchronous mode and 8/9-bit UART modes | |
-DAC to sense the Analog Input Level | |
-Two I2C Master and two I2C Slave ports with configurable pin outs | |
-DAC and External Interrupt pins can be additional GPIO if the associated function is not enabled | |
-Low Voltage Inhibit (LVI) circuit which provides reliable power up reset and prevent accidental data loss in Flash | |
● | Single 3.3V CMOS design |
● | 40-pin QFN (5mm x 5mm) package |