| 【 Features 】 |
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Embedded 32-bit RISC CPU core |
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-Operating frequency up to 192MHz |
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-2.41 DMIPS |
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-Boot from external serial flash |
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-DSP instruction set |
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-Internal 32KB DLM |
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-Internal 128KB ILM |
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-AXI to APB bridge |
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Memory |
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-External serial flash up to 128M bits |
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-640KB optimized internal frame buffers |
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Down sampling scaler with flexible scaling ratio (1 ~ 6) |
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-Bilinear method |
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Image mask (5x5 and 1x5) with user-defined coefficients |
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Grid remap |
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Perspective |
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Optical flow |
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-Lucas-Kanade (LK) optical flow algorithm |
| ● |
Features from accelerated segment test (FAST) corner detection |
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Connected component labeling (CCL) |
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Histogram 1D/2D calculation with polygon shape (MAX2D) |
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Optimized OpenVX engine |
| ● |
Sum of absolute differences (SAD) |
| ● |
Video inputs: |
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-ITU-601 / ITU-656 / ITU-1120 YUV |
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-Video formats: 720x480, 720x576, 1280x720p, 1920x1080p (30FPS) |
| ● |
Video outputs: |
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-ITU-601 / ITU-656 / ITU-1120 YUV |
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-Video formats: 720x480, 720x576, 1280x720p, 1920x1080p (30FPS) |
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-Analog CVBS output with internal video encoder (VDEN) |
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B/W stretch and histogram (YTUNE) |
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Brightness & contrast adjustment (BCA) |
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On screen display (OSD) |
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HD to SD resolution conversion |
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Frame buffer display (FB_DISP) |
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Communication interfaces |
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-1 master/slave mode I2C interfaces up to 400 kHz |
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-1 master/slave SPI up to 12 MHz |
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-2 full-duplex UART up to 1.5 MHz |
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-1 CAN bus up to 1 MHz |
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-Interface for ISP and ICE |
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Timer with 16-bit prescaler |
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GPIO with configurable input / output direction and pull-up / pull-down resistor |
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Window watchdog timer (WWDT) |
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2 PWM |
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CPU clock source |
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-External crystal oscillator 20 MHz to 27 MHz (built-in PLL) |
| ● |
Operating temperature range: -40℃ to +105℃ |
| ● |
Package type: |
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-VFBGA 112-ball (8 x 8 mm) |
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-LQFP-128 |
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